Important: For complete control
of your placement and USER_CLOCK_ROOT selection, Xilinx recommends that you create a Pblock that contains all of the loads
of your clock network. Then, assign the USER_CLOCK_ROOT to a clock region that contains
the vertical clock spine. In most cases, the Vivado
placer selects the optimal CLOCK_ROOT for your design, and the manual USER_CLOCK_ROOT
assignment is not necessary.
In some cases, the USER_CLOCK_ROOT assignment might be a suboptimal solution because it is not centered upon all loads and creates an unbalanced clock tree. In this case, the placer ignores the USER_CLOCK_ROOT constraint and assigns an optimal CLOCK_ROOT to the clock net.
For example, the USER_CLOCK_ROOT is set to X3Y2 but the loads are placed in X3Y3. In both clock regions, the vertical clock spine exists. However, the optimal solution is to use clock region X3Y3 for the CLOCK_ROOT. The placer issues a message to indicate the optimal solution.