PLL/MMCM Inverted Clocks - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English

In Versal devices, the MMCM does not have a CLKOUTxB port to generate the inverted clocks. To generate an inverted clock, a CLKOUTx output can be phase shifted by 180 degrees.

After the clock is phase shifted by 180 degrees, the timer models the phase shift either as a change in the clock waveform edges or as latency (without altering the clock waveform). You can control how the timer models the phase shift using the PHASESHIFT_MODE property on the MMCM. The default value for the PHASESHIFT_MODE property is LATENCY.

For more information, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

Note: DPLL and MMCM/XPLL configured with digital deskew only support PHASESHIFT_MODE=LATENCY.

When the phase shift is not used for I/O timing but for timing paths inside the fabric, the latency mode (PHASESHIFT_MODE=LATENCY) can result in unexpected setup/hold requirements between the non-phase-shifted clocks and the phase-shifted clock. This is the case when a clock is phase shifted by 180 degrees to generate an inverted clock for the fabric and replace the missing CLKOUTxB clocks in the Versal device.

Following are the options to generate the correct setup/hold requirements between a non-phase-shifted clock and a phase-shifted clock:

  • Add a multicycle path to adjust the clock edges used by the timer:
    set_multicycle_path -from [get_clocks clk] -to [get_clocks clk_phase_shitfed] -setup -end 0
  • Change the phase-shift model used by the timer from LATENCY to WAVEFORM. In this scenario, a multicycle path is not needed:
    set_property PHASESHIFT_MODE WAVEFORM [get_cells <MMCM>]