Xilinx recommends keeping the platform portion of your design to a minimum. For example, limit the RTL in the platform to the I/O only, and package functional RTL as a kernel. Minimizing the amount of logic in the platform reduces the overall number of platform iterations required to complete the design.
In general, Xilinx recommends handling computational or algorithmic logic blocks as kernels and keeping the following blocks in the platform:
- AI Engine
- I/O blocks (external pins, MIPI, PHY, etc.) and related IP (DMA for PCIe® , MAC for Ethernet, etc.)
The following table shows the recommended placement of each logic type, whether in the platform or in the kernel.
|AI Engine||Only in platform||Not supported|
|NoC||Only in platform||Not supported|
|Hard processors (PS8, CIPS)||Only in platform||Not supported|
|Soft processors ( MicroBlaze™ processors)||Preferred in platform||Acceptable as kernel|
|I/O block (external pins, MIPI, PHY, etc.)||Only in platform||Not supported|
|IP requiring Linux drivers and software stacks (VPSS, Ethernet MAC, DMA for PCIe, etc.)||Only in platform||Not supported|
|HLS IP with AXI interfaces||Acceptable in platform||Preferred as kernel|
|RTL IP with AXI interfaces||Acceptable in platform||Preferred as kernel|
|IP with non-AXI interfaces||Preferred in platform||Acceptable as kernel|
|Vitis libraries||Acceptable in platform||Preferred as kernel|