RTL Module References - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2022-05-25
Version
2022.1 English

You can add a module or entity definition from a Verilog, VHDL, or a BD RTL wrapper source file directly into your block design. This approach provides a way of quickly adding RTL modules without the need to package the RTL as an IP to be added through the Vivado IP catalog.

Any generics or parameters contained in the source RTL are inferred when the module is added to the block design, and can also be configured in the Re-customize Module Reference dialog box for a selected module. You must insert attributes into the HDL code so that interfaces, clocks, resets, interrupts, addresses, and clock enables are correctly inferred. For BD module references, these attributes are created automatically in the BD wrapper and are consumed when the BD module reference is created.

In addition, there is no parameter propagation across boundaries. You must use the attributes to support DRCs run by IP integrator when validating the design. For example, IP integrator provides DRCs for validating the clock frequency between the source clock and the destination. By specifying the correct frequency in the RTL code, you can ensure that your design connectivity is correct.

Following is important information to note when using RTL module references:

  • The Module Reference feature in the IP integrator allows inferencing of the XCI (.xci extension) files for IP embedded within the RTL code. Although most IP are supported for inferencing, a few are not. For more information, including a list of unsupported IP, see this link in the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).
  • The RTL module definition cannot include netlists (EDIF or DCP), or another module that is set as out-of-context (OOC) inside the RTL module.
  • VHDL and Verilog are the only supported languages for module definition. SystemVerilog and VHDL 2008 are not supported for the module or entity definition at the top-level of the RTL module.
  • A block design that contains a module reference cannot be packaged as an IP. Instead, you must package the module as an IP separately, and then package the BD including that IP.

The following figure shows the design hierarchy for a BD that contains two RTL module references: one reference that contains RTL and one that contains another BD.‚Äč

Figure 1. RTL Module References Design Hierarchy