Recommendations for Different Versal Device Design Topologies - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English

Following are the main design topologies for Versal devices:

  • RTL as top
  • BD as top
  • Classic SoC Boot

All Versal designs include some portion of the design in a block diagram because the CIPS and the NoC IP must be configured using a block design (BD). RTL as top and BD as top refer to how the block design is incorporated into the larger design. In an RTL as top design, the block diagram portion of the design is generated and stitched as a sub-module into the rest of the RTL hierarchy. In a BD as top design, the block diagram stitches together all of the design sources. These sources can be packaged and added to the block design as IP, or they can be referenced using RTL module referencing. Additional block designs can be incorporated into the top-level design using block design containers (BDCs).

Classic SoC Boot is a subset of the BD as top design topology and imposes additional requirements. In previous architectures, the DDRMC is owned directly by the processing sub-system. This allowed the processing sub-system to boot to Linux and subsequently program the PL, after the operating system was loaded. In Versal devices, the DDRMCs are shared resources and can be accessed over the NoC by several clients. This requires both the CIPS and NoC to be programmed for the CIPS to load the Linux kernel from the DDR memory. If this functionality is required, the CIPS and the NoC must be contained in a top BD, and the entire PL fabric portion of the design must be contained in a second block design. The PL block design must be instanced in the top block design using a block design container. Finally, the block design container must be marked as using DFX.

The most significant impact the design topology has on the overall project is the interaction between the hardware and software. When a BD as top design topology is used, all the information related to how the software must interact with the hardware is passed seamlessly through the hardware hand-off file. RTL does not yet provide a similar level of transparency. Following are recommendations for when to use each design topology:

  • RTL as top is recommended if you are comfortable manually creating the device tree and installing drivers for the design peripherals.
  • BD as top is recommended if you want a seamless hardware hand-off.
  • Classic SoC Boot is recommended if the design requires Linux booting first.