Reset Coding Example: Multiplier Pipeline Registers with Synchronous and Asynchronous Reset - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English

In this example, the pipeline registers have a mix of synchronous and asynchronous resets in the logic that targets the dedicated DSP resources, which cause suboptimal performance of DSP primitive mapping. The following figure shows a 16x16-bit DSP58-based multiplier using input pipeline registers with asynchronous reset and multiplier output registers with synchronous reset. Synthesis must use regular fabric registers for the input stages. The multiplier register with synchronous reset is packed into the DSP output (DSP58 M and P registers). This adds up to 32 extra fabric registers, and the DSP58 results in the configuration: AREG/BREG=0, MREG=1, PREG=1.

Figure 1. Multiplier with Pipeline Registers (Synchronous and Asynchronous Reset)

To take advantage of the existing DSP primitive features, you can rewrite the preceding example to change the mix of asynchronous reset and synchronous reset on pipeline registers into a single type of reset for all pipeline registers. The following figure shows how to change the reset definition in the RTL so that all of the pipeline registers around the multiplier logic use a single type of reset (synchronous/asynchronous reset). By making this change, synthesis can take advantage of the DSP58 internal registers (AREG/BREG=1, MREG=1, PREG=1).

Figure 2. Changing Synchronous and Asynchronous Reset into a Single Type of Reset for All Pipeline Stages Around Multiplier Logic