In Xilinx devices, all registers are built to
have set/reset take precedence over clock enable, whether an asynchronous or synchronous
set/reset is described. In order to obtain the most optimal result, Xilinx recommends that you always code the set/reset
before the enable (if deemed necessary) in the if/else
constructs within a synchronous block. Coding a clock enable first forces the reset into
the data path and creates additional logic.