| 05/25/2022 Version
2022.1 |
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Design Flow Diagrams
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Added new section. |
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Platform-Based Design Flow Best Practices
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Added table. |
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Design Planning Considerations for DFX based Vitis Acceleration Platform Development
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Added new section. |
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Design Planning Considerations for Classic SoC Boot
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Added new section. |
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Design Planning Considerations for Tandem Configuration
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Added new section. |
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Defining a Good Block Design Hierarchy
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Added new section. |
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Instantiating Block Designs
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Added benefits of each approach. |
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Using Different Source Files in IP Integrator
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Added design hierarchy diagrams for each section. |
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Recommendations for Designing with Versal Device IP
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Added new section. |
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Recommendations for Different Versal Device Design Topologies
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Added new section. |
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Checking for Feedback Structures in Registers
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Updated example. |
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Check Inferred Logic
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Added information on retiming_forward and retiming_backward. |
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XPIO Global Clock Buffer Clock Enable Timing
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Added new section. |
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Boundary Clock Nets
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Removed example. |
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SSI Technology Considerations for I/O Planning
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Added new section. |
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Designing with SSI Devices
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Added new chapter. |
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Using the Boundary Logic Interface Constraint
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Added new section. |
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Floorplanning Constraints for Dynamic Function eXchange
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Added recommendations and revised entire section. |
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Assessing Post-Synthesis Quality of Results
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Updated table. |
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NoC Compiler Runs During Placement
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Added information on global placement. |