When data flow requirements require that wide buses cross SLRs, use pipelining strategies to improve timing closure and alleviate routing congestion of long resources. For wide buses operating above 250 MHz, Xilinx recommends using at least three pipeline stages to cross an SLR: one at the top, one at the bottom, and one in the middle of the SLR. Additional pipeline stages might be required for very high performance buses or when traversing horizontal as well as vertical distances.
The following figure illustrates a worst case crossing for a VP1702 device. This example starts at an Interlaken dedicated block in the top right of SLR2 to a packet monitor block assigned to the bottom left of SLR0. Without pipeline registers for the data bus to and from the packet monitor, the design misses the 300 MHz timing requirement by a wide margin.
However, adding six pipeline stages to aid in the traversal from SLR2 to SLR0 allows the design to meet timing. It also reduces the use of vertical and horizontal long routing resources, as shown in the following figure.