When planning pinouts for a Versal ACAP stacked silicon interconnect (SSI) technology device, it is important to recognize that XPIO banks are located in the bottom SLR (SLR0) instead of spread throughout the SLRs as in previous columnar architectures. Logic associated with an XPIO external interface most likely exists in SLR0, and this logic must not cross SLRs. When deciding on the placement of an external interface, consider the following:
- For smaller interfaces, group all pins within a single XPIO bank.
- For larger interfaces, group all pins in multiple adjacent XPIO banks.
- Place hardened DDR memory controllers in the corner banks that do not have PL access.
- Balance clock-capable I/O (CCIO) or clock management tile (CMT) components across XPIO banks.