Traditional Design Flow for Hardware-Only Systems - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2022-05-25
Version
2022.1 English

If your design consists of PL components only (RTL and IP only), you can use the Vivado® tools to generate a programmable device image (PDI) to program the Versal device. Like previous architectures, design sources are added to the Vivado tools and compiled through the Vivado implementation flow.

Important: The platform management controller (PMC) is incorporated into the CIPS IP and must be configured for the Versal device to boot properly. Therefore, all Versal device designs must include CIPS IP.

Following are additional important considerations:

  • The hardened DDR memory controllers are only accessible through the NoC IP. To use the DDRMC, your design must include NoC IP.

  • Hardware debug cores connect through the CIPS IP by default. JTAG is still available but no longer the preferred flow. You must be familiar with changes to the hardware debug connectivity and flow.

You must use the Vivado IP integrator to instantiate, configure, and connect the CIPS IP, the NoC/DDRMC IP, and hardware debug IP to take advantage of block design automation when iterating through design changes. The Vivado IP integrator also provides special support for GT IP and connectivity IP (such as MRMAC IP), which simplifies GT-based design creation and I/O planning.

You can integrate the complete design with the Vivado IP integrator using custom packaged IP, RTL module referenced blocks, and other IP available through the IP catalog. Alternatively, you can use the Vivado IP integrator to configure and connect critical Versal ACAP IP (such as the CIPS IP and the NoC/DDR IP) and then instantiate the resulting block design in the RTL design. For more information, see this link in the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).

Note: The Vivado IP integrator is supported in Project Mode only.
Important: This design flow does not support programming of the AI Engine cores and is therefore only suitable for Versal Prime and Versal Premium devices.