The IP integrator uses a variety of sources, including the Xilinx® IP catalog, other block designs, custom packaged IP, and referenced RTL modules. The sources must be used correctly to simplify the design structure and improve individual and team productivity. The following table summarizes key advantages and disadvantages associated with different sources.
|Catalog IP||Custom Packaged IP||Packaged Block Design||Block Design Container||RTL Module Reference|
|Description||Off-the-shelf configurable IP||Converts HDL modules into reusable IP blocks||Converts BDs into reusable custom packaged IP||Allows instantiation of a BD within another BD||Allows HDL or another BD to be added directly to a BD|
|Advantages||Tested and verified IP blocks||
||Legacy method to reuse a BD
Note: For new designs, BDCs are preferred.
||Quick way to add RTL or nest a single BD without IP packaging effort|
|Limitations||Customization limited to available IP settings without option to modify IP sources||Inability to view or modify from top BD||Packaged BD contains fixed addressing information||Nested BD not yet supported
Note: For more information, see Xilinx Answer Record 75853.
|Design checkpoints or additional nested module references are not allowed in the RTL files|
|Ability to Reuse||High||High||Low||High||Medium|
The following sections highlight methodologies that best leverage these sources and IP integrator capabilities to improve the structure and integration of complex Versal ACAP designs.