To constrain clocks, you can assign placement constraints as follows:
- On a clock input at the I/O port
Assigning a PACKAGE_PIN constraint for a clock on a GCIO or assigning a LOC to an IOB affects the clock network. The MMCM/XPLL/DPLL and clock buffers directly connected to the input port must be placed in the same clock region.
- On MMCM/XPLL/DPLLs
The clock buffers directly connected to the MMCM/XPLL/DPLL outputs and the input clock ports connected to the MMCM/XPLL/DPLL inputs are automatically placed in the same clock region. If an input clock port and an MMCM/XPLL/DPLL are directly connected and constrained to different clock regions, you must manually insert a clock buffer and set a CLOCK_DEDICATED_ROUTE constraint on the net connected to the MMCM/XPLL/DPLL.
- On a GT*_QUAD or IBUFDS_GT* cell
The BUFG_GTs driven by the cell are placed in the same clock region.