Flip-flop stages exist in the boundary logic interface (BLI) between the programmable logic (PL) and the high-performance XPIO and between the PL and AI Engine interface tiles. The BLI flip-flop resources can optimize the interface timing by registering signals coming into and going out of the PL. BLI flip-flop resources have the following restrictions:
- BLI only supports flip-flops with asynchronous clear (FDCE) or a synchronous reset (FDRE) with the R-pin tied to GND.
- BLI only supports FDCE and FDRE with INIT value of 0.
- All BLI flip-flops in a site must share the same active CLR signal or inactive GND R signal.
- FDCE and FDRE can be mixed in a site only if the CLR pin and R-pins are tied to GND.
- All BLI flip-flops in a site must share the same CE signal.
By default, flip-flops are not placed in BLI flip-flop resources if the flip-flops are simply connected to an XPIO bank or AI Engine interface tile resources. The BLI constraint must be used for the Vivado tools to place flip-flops in the BLI flip-flop resources. If the BLI constraint cannot be met due violation of the restrictions, the flip-flop is placed in the PL. Nets of PL flip-flops interfacing with resources using the BLI perform a route-through of the BLI flip-flop resources. In the following example, the BLI constraint is used for flip-flops in BLI resources driving a flip-flop in the XPIO IOB. The example also demonstrates a PL flip-flop driving a flip-flop in the XPIO IOB and shows the route from the BLI through the BLI flip-flop resources.
set_property BLI TRUE [get_cells myIntf/myBLI_reg]