You can use the CLOCK_REGION constraint to assign a clock buffer to a clock region without specifying a site. This gives the placer more flexibility when optimizing all the clock trees and when determining the appropriate buffer sites to successfully route all clocks.
You can also use a CLOCK_REGION constraint to provide guidance on the placement of cascaded clock buffers or clock buffers driven by non-clocking primitives, such as fabric logic.
In the following example, the XDC constraint assigns the clkgen/clkout2_buf clock buffer to the XPIO bank CLOCK_REGION X3Y0.
set_property CLOCK_REGION X3Y0 [get_cells clkgen/clkout2_buf]