Because Vitis HLS allows generation of the hardware design from C/C++ source code, Vitis HLS is recommended for software developers who need to create PL blocks in a Versal ACAP project. However, writing C/C++ for hardware is different from writing C/C++ for software, because Versal devices have different underlying architectures from CPUs or even GPUs. Therefore, it is important to use programming patterns optimized for Versal devices. The producer-consumer pattern is especially well-suited for Versal device programming. If you are not familiar with this concept or with the concepts of data streaming and pipelining, see this link in the Vitis HLS User Guide (UG1399).