Even at lower frequencies, it might be difficult to meet the setup timing to the global clock buffer enable pin. The setup timing incurs a late data arrival due to the enable control logic flip-flop being driven by a global clock buffer and the route from flip-flop crossing the boundary logic interface (BLI) to reach the enable pin. The setup timing incurs an early data required time due to the clock arriving directly at the gated global clock buffer input pin without having traversed the global clock network.
You can use the following techniques to improve timing to the global clock buffer enable pins:
- Use the HARDSYNC feature on the global clock buffers that use a three-stage internal synchronizer. This removes the timing requirement but incurs a three or four clock-cycle latency on the clock output.
- Use a negative phase-shifted clock to drive the enable control logic.
- Use the CLOCK_LOW_FANOUT constraint on the clock used to drive the enable control logic. This reduces the clock insertion delay on the source clock path.
- Use the BLI constraint on the flip-flop that directly drives the global clock buffer. The BUFGCE clock enable pins do not have an associated BLI flip-flop resource. Therefore, you must use a BUFGCE_DIV with a divide of 1 or a BUFGCTRL when using the BLI flip-flop.
- Use a cascaded buffer to drive the gated clock buffer and ensure the
- Cascaded buffer is not optimized away
- Cascaded buffer is placed in the same CLOCK REGION as the gated clock buffer
- Cascaded buffer and buffer driving the enable control logic are balanced