Generating kernels from C/C++ code for use in the Vitis core development kit follows the standard Vitis HLS process. However, because the kernel is required to operate in the Vitis software platform, the standard kernel requirements must be satisfied (see PL Kernel Properties). Most importantly, the interfaces must be modeled as AXI memory interfaces, except for scalar parameters which are mapped to an AXI4-Lite interface. Vitis HLS automatically defines the interface ports to meet the standard kernel requirements when using the Vitis Bottom Up Flow as described here.
The process for creating and compiling your HLS kernel is outlined briefly below. You should refer to Creating a New Vitis HLS Project in the Vitis HLS Flow documentation for a more complete description of this process.
- Launch Vitis HLS to open the integrated design environment (IDE), and specify .
- In the New Vitis HLS Project wizard, specify the Project name, define the Location for the project, and click Next.
- In the Add/Remove Files page, click Add Files to add the kernel source code to the project. Select Top Function to define the kernel function by clicking the Browse button, and click Next when done.
- You can specify a C-based simulation test bench if you have one available,
by clicking Add Files, or skip this by
clicking Next.Tip: As discussed in the Vitis HLS documentation, the use of a test bench is strongly recommended.
- In the Solution
Configuration page, you must specify the
Clock Period for the
- Choose the target platform by clicking the browse button (…) in the Part Selection field to open the Device Selection dialog box. Select Boards, and select the target platform for your compiled kernel, as shown below. Click OK to select the platform and return to the Solution Configuration page.
- In the Solution
Configuration page, select the Vitis Kernel Flow Target drop-down menu under Flow Target, and click Finish to complete the process and create your HLS
kernel project.Important: You must select the Vitis Kernel Flow Target to generate the Xilinx object (XO) file from the project.
When the HLS project has been created you can Run C-Synthesis to compile the kernel code. Refer to the Vitis HLS documentation for a complete description of the HLS tool flow.
After synthesis is completed, the kernel can be exported as an XO file for use in the Vitis core development kit. The export command is available through the command from the main menu.
Specify the file location, and the kernel is exported as a Xilinx object XO file.
The (XO) file can be used as an input file during the
v++ linking process. Refer to Linking the Kernels for more information. You can also add it to an
application project in the Vitis IDE, as discussed
in Creating a Vitis IDE Project.
However, keep in mind that HLS kernels, created in the bottom-up flow described here, have certain limitations when used in the Vitis application acceleration development flow. Software emulation is not supported for applications using HLS kernels, because duplicated header file dependencies can create issues. GDB debug is not supported in the hardware emulation flow for HLS kernels, or RTL kernels.