As discussed in Running Multiple Implementation Strategies for Timing Closure, the
v++ linking step can run multiple iterations of Vivado implementation using different strategies to
achieve timing closure. Vitis analyzer can visualize
and compare these results from multiple implementation attempts. As explained, the
Vitis compiler automatically picks the first
completed run that meets timing to proceed with the build and generate the device binary
(xclbin). This includes logging the report
files for that one run only. However, you can have the Vitis compiler wait until all of the implementation runs are complete
before proceeding to generate an xclbin file. In
this case, results for each implementation run are available in the
link_summary for your review and comparison in Vitis analyzer.
Link Summaries with multiple implementation strategies display each strategy in the Report Navigator pane, as shown in the figure below. Each of these strategies include a Timing Summary report. Even though the xclbin is generated for only one strategy, the Link Summary reports are available for all implementation runs to extract useful resource and timing information.
The Timing Summary report in Vitis analyzer is a simplified version of the complete Timing Summary report generated by Vivado place and route. The simplified report only displays the worst setup, hold, and pulse width paths for the design. You can view this report without needing to open a Vivado project or netlist, so you can quickly navigate to failing timing paths. The details are displayed in the report viewer as shown below. The Timing Summary is displayed, as well as detailed path reports for the worst Setup, Hold, and Pulse Width observed in the design. To see the complete timing report, click the T toolbar button, which displays the text version of the report.