.xo) file whether the kernel is written in C/C++, OpenCL C, or RTL. During the linking stage, XO files from different kernels are linked with the platform to create the FPGA binary container file (.xclbin), or the hardware definition file (.xsa) used by the Vitis packaging process as described in Packaging the System.
v++ --linkcommand generates a hardware definition file (.xsa) for Versal® device platforms (i.e. vck190, vck5000), for use by the
v++ --packagecommand to generate the .xclbin file. For Alveo™ data center accelerator cards, and embedded processor cards the
v++ --linkcommand generates an .xclbin file directly, though the
v++ --packagecommand might still be needed.
Similar to compiling, linking requires several options. The following is
an example command line to link the
v++ -t hw_emu --platform xilinx_u200_gen3x16_xdma_2_202110_1 --link vadd.xo -o'vadd.sw_emu.xclbin' \ --config ./system.cfg
This command contains the following arguments:
- Specifies the build target. Software emulation (
sw_emu) is used as an example. When linking, you must use the same
--platformarguments as specified when the input (XO) file was compiled.
- Specifies the platform to link the kernels with. To link the
kernels for an embedded processor application, you simply specify an embedded
- Link the kernels and platform into an FPGA binary file (xclbin).
- Input object file. Multiple object files can be specified to build into the .xclbin.
- Specify the output file name. The output file in the link stage will be an .xsa file. The default output name is a.xsa.
- Specify a configuration file that is used to provide
v++command options for a variety of uses. Refer to Vitis Compiler Command for more information on the
v++ -t hw_emu --platform xilinx_vck190_base_202210_1 --link vadd.xo -o"binary_container_1.xsa" \ --config ./system.cfg
After the linking step is complete, any reports generated during this process are collected into the <kernel_name>.link_summary. This collection of reports can be viewed by opening the link_summary in Vitis analyzer, and includes a Summary report, System and Platform Diagrams to illustrate the hardware design, System Estimate providing timing and resources estimates, System Guidance offering any suggestions for improving linking and the performance of the system, and the Vivado Automation Summary providing design details such as interface connections, clocks, resets, and interrupts. Refer to Using the Vitis Analyzer for additional information.
Beyond simply linking the Xilinx object (XO) files, the linking process is also where important architectural details of the design are specified. In particular, this is where the design is enabled for profiling or debug, where you specify the number of compute unit (CUs) to instantiate into hardware, where CUs are assigned to SLRs, and where you define connections from kernel ports to global memory or between streaming ports. The following sections discuss some of these build options.