The base design you created in a Vitis platform is static after the platform creation process is complete.
Vitis does modify parameters based on certain IPs (for example, SmartConnect, NoCs) by adding additional master/slave interfaces. In some situations, PS/CIPS interfaces can also be modified and Versal® ACAP andAI Engine IP is instantiated in the platform.
The following table shows the workflows to validate the base system on your board.
|Basic board bring-up||Processor basic parameter setup.||Standalone Hello world and Memory Test application run properly.|
|Advanced hardware setup||Enable advanced I/O in Processing System (such as USB, Ethernet, Flash,
, or RC).
Add I/O related IP in PL (such as MIPI, EMAC, or HDMI_TX).
Add non-Vitis IP (such as AXI BRAM Controller, or Video Processing Subsystem (VPSS) IP).
|If these IP have standalone drivers, test them.|
|Base software setup||Create PetaLinux project based on hardware platform.
Enable kernel drivers.
Configure boot mode.
|Linux boots up successfully.
Peripherals work properly in Linux.
Base Component Requirements
Every hardware platform design must contain a Processing System IP block from the IP catalog.
- Versal ACAP, Zynq® UltraScale+™ MPSoC, and Zynq-7000 SoC devices are supported.
- MicroBlaze™ processors are not supported for controlling acceleration kernels, but can be part of the base hardware.