The convolutional filter example is based on a video filtering use case. An image filter is applied to all the channels of a video frame. The host generates a stream of images for each color channels which are transferred to the device for processing. The RGB video has three parallel channels providing coarse-grain parallelism which allows to process three color channels independently using a separate compute unit per channel. The problem is to design an FPGA based video filter where each video channel can be processed in parallel by a separate CU. The convolutional filter applied to each channel is the same so it is possible that you can build a single compute unit and use three instances of the CU for acceleration. The following sections describe in detail how the host side and CU are modeled and implemented using the Vitis System Compilation (VSC) mode.