Getting Started with Vitis Revision History
The following table shows the revision history for Getting Started with Vitis.
| Section | Revision Summary |
|---|---|
| 05/25/2022 Version 2022.1 | |
| Installing the Vitis Software Platform | Removed a note. |
| Accelerated Flow Application Development Using the Vitis Software Platform | Updated bullet list. |
| Execution Model | Updated the section. |
| Data Center Application Acceleration Development Flow | Added a tip about System Complication Mode. |
| 04/26/2022 Version 2022.1 | |
| N/A | No changes to this section. |
Introduction to Vitis Flows Revision History
The following table shows the revision history for Introduction to Vitis Flows.
| Section | Revision Summary |
|---|---|
| 05/25/2022 Version 2022.1 | |
| Working with Alveo Accelerator Cards | Updated the section. |
| Introduction to Data Center Acceleration for RTL Designers | New section added. |
| 04/26/2022 Version 2022.1 | |
| Entire section | New section added. |
Developing Applications Revision History
The following table shows the revision history for Developing Applications.
| Section | Revision Summary |
|---|---|
| 05/25/2022 Version 2022.1 | |
| Kernel Interfaces | Updated the section. |
| 04/26/2022 Version 2022.1 | |
| N/A | No changes to this section. |
Building and Running the Application Revision History
The following table shows the revision history for Building and Running the Application.
| Section | Revision Summary |
|---|---|
| 05/25/2022 Version 2022.1 | |
| Enabling Profile and Debug when Linking | Updated the section. |
| Using the -vivado and -advanced Options | Updated the section. |
| Writing Traffic Generators in SV/Verilog | Added an image. |
| How to Use the create/use xtlm_ipc_verilog_stub Module | Added new topic. |
| 04/26/2022 Version 2022.1 | |
| Linking the Kernels |
v++
--link now generates an XSA file for Versal devices rather than an
XCLBIN file. Use v++ --package to
generate the XCLBIN. |
| Enabling Profile and Debug when Linking | New topic that summarizes options for enabling profiling and debug. |
| HBM Configuration and Use | New syntax for adding RAMA IP. |
| Random Access and the RAMA IP | Updated syntax for adding RAMA IP to HBM memory mapping. |
| Assigning Compute Units to SLRs | Added information related to assigning CUs to SLRs. |
| Identifying Platform Clocks | Updated description of fixed and scalable clocks. |
| Packaging the System |
v++
--link now generates an XSA file for Versal devices rather than an
XCLBIN file. Use v++ --package to
generate the XCLBIN. |
| Packaging for Embedded Platforms | See above. |
| Packaging for Data Center Platforms | See above. |
| AXI Transactions Display in XSIM Waveform | Specified method for adding signals to waveform |
| Working with Functional Model of the HLS Kernel | Describes how to use C-models for hardware emulation. |
Profiling, Optimizing, and Debugging the Application Revision History
The following table shows the revision history for Profiling, Optimizing, and Debugging the Application.
| Section | Revision Summary |
|---|---|
| 05/25/2022 Version 2022.1 | |
| Baselining Functionality and Performance | Updated the section. |
| Generating and Opening the Waveform Reports | Updated Running Emulation link. |
| Interpreting Data in the Waveform Views | Added HLS Process and HLS FIFO sections. |
| Kernel SLR and DDR Memory Assignments | Updated the section. |
| 04/26/2022 Version 2022.1 | |
| N/A | No changes to this section. |
Vitis Environment Reference Materials Revision History
The following table shows the revision history for Vitis Environment Reference Materials.
| Section | Revision Summary |
|---|---|
| 05/25/2022 Version 2022.1 | |
| N/A | No changes to this section. |
Using the Vitis Analyzer Revision History
The following table shows the revision history for Using the Vitis Analyzer.
| Section | Revision Summary |
|---|---|
| 05/25/2022 Version 2022.1 | |
| N/A | No changes to this section. |
| 04/26/2022 Version 2022.1 | |
| Working with Summary Reports | Added new Automation Summary to link_summary report. |
| Compare Two Timeline Trace Reports | Added description of Save Filter As command. |
Using the Vitis IDE Revision History
The following table shows the revision history for Using the Vitis IDE.
| Section | Revision Summary |
|---|---|
| 05/25/2022 Version 2022.1 | |
| G++ Host Compiler and Linker Settings | Updated the section. |
| Streaming Interfaces | Removed host operations. |
| Using the RTL Kernel Project in Vivado IDE | Removed block design. |
| Generate RTL Kernel | Updated the section. |
| 04/26/2022 Version 2022.1 | |
| General Settings | No changes to this section. |
Using Vitis Embedded Platforms Revision History
The following table shows the revision history for Using Vitis Embedded Platforms.
| Section | Revision Summary |
|---|---|
| 05/25/2022 Version 2022.1 | |
| N/A | No changes to this section. |
| 04/26/2022 Version 2022.1 | |
| N/A | No changes to this section. |
Using Vitis System Compilation Mode Revision History
The following table shows the revision history for Using Vitis System Compilation Mode.
| Section | Revision Summary |
|---|---|
| 05/25/2022 Version 2022.1 | |
| Entire section. | New section added. |
Additional Information
The following table shows the revision history for Additional Information.
| Section | Revision Summary |
|---|---|
| 05/25/2022 Version 2022.1 | |
| N/A | No changes to this section. |
| 04/26/2022 Version 2022.1 | |
| Coding Guidelines for Free-Running Kernels | |