- PL or Programmable Logic
- The part of the FPGA that is made of fundamental
programmable building blocks such as flip-flops registers, look-up-tables
(LUTs), digital signal processing units (DSPs), RAM-based memory block or
clocking circuitry. The PL region can contain one or more accelerators as
defined below.
- Accelerator (ACC)
- Designates everything that is custom-generated by the VSC
mode and sits inside the programmable logic of the FPGA or ACAP device. The
accelerator contains one or more replicated compute units (CUs) in the
hardware. In some situations, the term accelerator might also be loosely
used to describe the whole Programmable Logic design also including the
platform and/or
.xo kernels generated by
the Vitis compile flow. The VSC
accelerator is specified in a user-defined C++ class derived from a
predefined VPP_ACC class. The interface
specification contains connections into Vitis platform ports to access the peripheral resources such
an global memories or ethernet ports. The accelerator also contains data
movers, which are IP designed to efficiently move data from global memory to
the compute units and back.
- Compute Unit (CU)
- Designates the composition of one or more processing
elements (PEs) as defined below, that connect to global memory and streams
to move data to other PEs. The interface is described using the
compute() method in the accelerator class.
This named API acts as the software entry-point function to the accelerator
and therefore specifies the hardware-software arguments. The CU makes the
system composition self-describing from the source code and not via the use
of text config files.
- Processing Element (PE)
- Designates the core building block of a compute
functionality that performs specific actions on data. This is a
function-call within the scope of the of the
compute() method in the accelerator class. The processing
element's functionality can be written in C++ and each PE is compiled by
individually by Vitis HLS.
- Compose/Composition
- Refers to a method of assembling PEs to form a structural
network for a CU. The body of the
compute() method semantically refers to a composition of PEs
in hardware, which is unlike the procedural semantics of a C-function body.
VSC will enable validation of such a specification. The PEs collectively
compose a CU, and one or more replicated CUs exist in an accelerator.