Generate traffic using the existing test bench written in the System Verilog/Verilog with slight modification to your test bench hierarchy, as explained below.
Figure 1. Test Bench Hierarchy
As shown in the figure above, the external test bench (on the left) and the Vitis emulation (on the right), both run as separate simulation processes. To establish communication between two processes using IPC, you must instantiate SIM_IPC Master/Slave modules.
Perform the following modifications:
- Add IPC modules in the Vitis
emulation design. These are available as prepackaged XOs, and you can insert them
using the
v++
command line as described in AXI4-Stream I/O Model for Streaming Traffic. - Add SIM IPC modules in your SV/V test bench. Instantiate the
ipc_axis_master_mirror
module inside the Traffic Generator top and make the pin level connection via an SV interface. Theipc_axis_master_mirror
converts the pin level AXI transactions togeneric_payload
and sends through the IPC sockets to theipc_axis_master
module in the Vitis emulation design. Similarly, there is anipc_axis_slave_mirror
module that is instantiated in the Traffic Generator top to connect to theipc_axis_slave
module in the Vitis emulation design.
The same technique can be deployed to drive traffic from the external System Verilog/Verilog traffic generators/test benches to the AI Engine simulator or x86-simulator.
Figure 2. XTLM Test Bench Hierarchy
Note: The module used to send data to/from
external TG to Emulation process/ AI Engine simulator/xx86-sim can be named differently in
different simulation contexts, such that the following is true:
-
xtlm_ipc_pl2aie
oripc_axis_master_mirror
is the same -
tlm_ipc_aie2pl
oripc_ais_slave_mirror
is the same - Collectively, these are xtlm_ipc_verilog_stub modules. All names are interchangeable.