In the Vivado IP flow Vitis HLS synthesizes arrays into memory elements by default. When you use an array as an argument to the top-level function, Vitis HLS assumes one of the following:
- Memory is off-chip.
Vitis HLS synthesizes interface m_axi ports to access the memory.
- Memory is standard block RAM with a latency of 1.
The data is ready one clock cycle after the address is supplied.
To configure how Vitis HLS creates these ports:
- Specify the interface as a M_AXI, BRAM, or FIFO interface using the INTERFACE pragma or directive.
- Specify the RAM as a single or dual-port RAM using the
storage_typeoption of the INTERFACE pragma or directive.
- Specify the RAM latency using the
latencyoption of the INTERFACE pragma or directive.
- Use array optimization directives, ARRAY_PARTITION, or ARRAY_RESHAPE, to reconfigure the structure of the array and therefore, the number of I/O ports.
d_iin Array Interfaces is changed to
d_i, Vitis HLS issues a message that the design cannot be synthesized:
@E [SYNCHK-61] array_RAM.c:52: unsupported memory access on variable 'd_i' which is (or contains) an array with unknown size at compile time.