During synthesis several optimizations, such as strength reduction and bit-width minimization are performed. Included in the list of automatic optimizations is expression balancing.
Expression balancing rearranges operators to construct a balanced tree and reduce latency.
- For integer operations expression balancing is on by default but may be disabled using the EXPRESSION_BALANCE pragma or directive.
- For floating-point operations, expression balancing is off by default but may be
enabled using using the
config_compile -unsafe_math_optimizationscommand, as discussed below.
Given the highly sequential code using assignment operators such as
in the following example (or resulting from loop unrolling):
data_t foo_top (data_t a, data_t b, data_t c, data_t d)
sum = 0;
sum += a;
sum += b;
sum += c;
sum += d;
Without expression balancing, and assuming each addition requires one
clock cycle, the complete computation for
requires four clock cycles shown in the following figure.
can be executed in parallel allowing the latency to be reduced. After
balancing the computation completes in two clock cycles as shown in the
following figure. Expression balancing prohibits sharing and results
in increased area.
For integers, you can disable expression balancing using the EXPRESSION_BALANCE
optimization directive with the
By default, Vitis HLS does not perform the
EXPRESSION_BALANCE optimization for operations of type
double. When synthesizing
Vitis HLS maintains the order of
operations performed in the C/C++ code to ensure that the results are the
same as the C/C++ simulation. For example, in the following code example,
all variables are of type
double. The values of
are not the same even though they appear to perform the same basic
This behavior is a function of the saturation and rounding in the C/C++ standard
when performing operation with types
double. Therefore, Vitis HLS always maintains the exact order
of operations when variables of type
double are present and does not perform
expression balancing by default.
You can enable expression balancing for specific operations, or you can configure
the tool to enable expression balancing with
-unsafe_math_optimizations command as follows:
- In the Vitis HLS IDE, select .
- In the Solution Settings dialog box, click the General category, select config_compile, and enable unsafe_math_optimizations.
With this setting enabled, Vitis HLS might change the order of operations to produce a more optimal design. However, the results of C/RTL co-simulation might differ from the C/C++ simulation.
unsafe_math_optimizations feature also
no_signed_zeros optimization ensures
that the following expressions used with
x - 0.0 = x;
x + 0.0 = x;
0.0 - x = -x;
x - x = 0.0;
x*0.0 = 0.0;
no_signed_zeros optimization the
expressions above would not be equivalent due to rounding. The optimization
may be optionally used without expression balancing by selecting only this
option in the
no_signed_zero optimizations are used, the RTL
implementation will have different results than the C/C++ simulation. The
test bench should be capable of ignoring minor differences in the result:
check for a range, do not perform an exact comparison.