By default input pointers and pass-by-value arguments are implemented as
simple wire ports with no associated handshaking signal. For example, in the
vadd function discussed in Interfaces for Vivado IP Flow, the input ports are implemented without an I/O
protocol, only a data port. If the port has no I/O protocol, (by default or by design)
the input data must be held stable until it is read.
vadd function example, the output port is implemented with an associated
output valid port (
out_r_o_ap_vld) which indicates
when the data on the port is valid and can be read. If there is no I/O protocol
associated with the output port, it is difficult to know when to read the data.
Function arguments which are both read from and written to are split into
separate input and output ports. In the
out_r argument is implemented as both an
out_r_i, and an output port
out_r_o with associated I/O protocol port
If the function has a return value, an output port
ap_return is implemented to provide the return value. When
the RTL design completes one transaction, this is equivalent to one execution of the
C/C++ function, the block-level protocols indicate the function is complete with the
ap_done signal. This also indicates the data on
ap_return is valid and can be read.
For the example code shown the timing behavior is shown in the following figure (assuming that the target technology and clock frequency allow a single addition per clock cycle).
- The design starts when
ap_startis asserted High.
ap_idlesignal is asserted Low to indicate the design is operating.
- The input data is read at any clock after the first cycle. Vitis HLS schedules when the reads occur. The
ap_readysignal is asserted High when all inputs have been read.
- When output
sumis calculated, the associated output handshake (
sum_o_ap_vld) indicates that the data is valid.
- When the function completes,
ap_doneis asserted. This also indicates that the data on
ap_idleis asserted High to indicate that the design is waiting start again.