Reserved memory has been defined by the hardware and software programming environment for privileged use. This is typically true for memory containing interrupt vector locations and operating system level routines. The following table lists the reserved memory locations for MicroBlaze and Arm processors as defined by the processor hardware. For more information on these memory locations, refer to the corresponding processor reference manuals.
For information about the Arm Cortex A9 memory map, refer to the Zynq-7000 SoC Technical Reference Manual (UG585). For the Cortex-R5F, Cortex-A53, and Cortex-A72 memory map, refer to the Zynq UltraScale+ Device Technical Reference Manual (UG1085).
|Processor Family||Reserved Memories||Reserved Purpose||Default Text Start Address|
|MicroBlaze||0x0 - 0x4F||Reset, Interrupt, Exception, and other reserved vector locations.||0x50|