Target Setup Page - 2022.1 English

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)

Document ID
Release Date
2022.1 English

Provide a unique name for your configuration. Next, in the Main view, set up the following details:

FPGA Device
This is automatically selected for you.
PS Device
This is automatically selected for you.
Hardware Platform
Select the hardware platform for your design.
Bitstream file
Search or browse to your Bitstream file.
FSBL File or Initialization File
Selects either the FSBL file or Initialization file based on whether the checkbox is selected. By default, the Use FSBL Flow for Initialization check-box is checked (ZYNQ and ZYNQ UltraScale+ Only).
Reset Entire System
Perform a system reset if there is only one processor in the system.
Initialize Using FSBL file
Initialize PS using FSBL file.
Reset APU
Reset all the APU processor cores.
Reset RPU
Reset all the RPU processor cores.
Enable RPU Split Mode
Put RPU cores in split mode so that they can be used independent of each other.
Program FPGA
To program the bit file.
Skip Revision Check
Enabling this option will skip the device revision while programming bitstream.