Block Parameters for the JTAG Hardware Co-Simulation Block - 2022.1 English

Vitis Model Composer User Guide (UG1483)

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2022.1 English

The block parameters dialog box for the JTAG hardware co-simulation block can be invoked by double-clicking the block icon in your Simulink model.

Parameters specific to the block are as follows:

Basic tab

Has combinational path: Select this if your circuit has any combinational paths. A combinational path is one in which a change propagates from input to output without any clock event. There is no latch, flip-flop, or register in the path. Enabling this option causes Model Composer to read the outputs immediately after writing inputs, before clocking the design. This ensures that value changes on combinational paths extending from the hardware co-simulation block into the Simulink Model get propagated correctly.

Bitstream file: Specify the FPGA configuration bitstream. By default this field contains the path to the bitstream generated by Model Composer during the last Generate triggered from the System Generator Token.

Advanced tab

Skip device configuration: When selected, the configuration bitstream will not be loaded into the FPGA or SoC. This option can be used if another program is configuring the device (for example, the Vivado Hardware Manager and the Vivado Logic Analyzer).

Display Part Information: This option toggles the display of the device part information string (for example, xc7k325tffg900-2 for a Kintex device) in the center of the hardware co-simulation block.

Cable tab

Cable Settings

Currently, Auto Detect is the only setting for this parameter. Model Composer will automatically detect the cable type.