Compilation Results - 2022.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2022-05-26
Version
2022.1 English

This topic discusses the low-level files Model Composer produces when HDL Netlist is selected on the System Generator token and Generate is clicked. The files consist of HDL that implements the design. In addition, Model Composer organizes the HDL files, and other hardware files into a Vivado® IDE Project. All files are written to the target directory specified on the System Generator token. If no test bench is requested, then the key files produced by Model Composer are the following:

Table 1. Compilation Files
File Name or Type Description
<design_name>.vhd/.v This file contains a hierarchical structural netlist along with clock/clock enable controls
<design_name_entity_declarations>.vhd/.v This file contains the entity of module definitions of HDL blocks in the design.
<design_name>.xpr This file is the Vivado IDE project file that describes all of the attributes of the Vivado IDE design.

If a test bench is requested, then, in addition to the above, Model Composer produces files that allow simulation results to be compared. The comparisons are between Simulink® simulation results and corresponding results from Questa, or any other RTL simulator supported by Vivado® IDE such as Vivado simulator, or VCS. The additional files are as follows:

Table 2. Additional Compilation Files
File Name or Type Description
Various .dat files These contain the simulation results from Simulink.
<design_name>_tb.vhd/.v This is a test bench that wraps the design. When simulated, this test bench compares simulation results from the digital simulator against those produced by Simulink.