There are different ways in which Model Composer can compile your design into an equivalent, often lower-level, representation. The way in which a design is compiled depends on settings in the System Generator Token dialog box. The support of different compilation types provides you the freedom to choose a suitable representation for your design's environment. For example, an HDL Netlist or IP catalog is an appropriate target if your design is used as a component in a larger system.
|HDL Netlist Compilation||Describes how to generate HDL files that implement the design.|
|Hardware Co-Simulation Compilation||Describes how Model Composer can be configured to compile your design into FPGA hardware that can be used by Simulink® and Questa.|
|IP Catalog Compilation||
Describes how to package a Model Composer design as an IP core that can be added to the Vivado® IP catalog for use in another design.
Model Composer uses the IP catalog compilation type as the default generation target.
|Synthesized Checkpoint Compilation||Describes how to generate a synthesized checkpoint file