Compiling a Model for Hardware Co-Simulation - 2022.1 English

Vitis Model Composer User Guide (UG1483)

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2022.1 English

The starting point for hardware co-simulation is the Model Composer model or subsystem you would like to run in hardware. A model can be co-simulated if it meets the requirements of the underlying hardware board. The model must include a System Generator token; this block defines how the model should be compiled into hardware.

For information on how to use the System Generator token, see Compiling and Simulating Using the System Generator Token.

To compile your Model Composer model for hardware co-simulation, perform the following:

  1. Double-click the System Generator token to open the System Generator token dialog box.
    Figure 1. System Generator Token Dialog Box

  2. In the Compilation tab, select a Board and a version of the board.

    The boards appearing in the Board list are:

    • All of the boards installed as part of the Vivado.
    • Any custom boards you have created in the Vivado.
    • Any Partner boards you have purchased and enabled in the Vivado.

    For a Partner board or a custom board to appear in the Board list, you must configure Model Composer to access the board files that describe the board. Board awareness in Model Composer is detailed in Specifying Board Support in Model Composer HDL Blockset.

    To compile for hardware co-simulation, you must select a Board. You cannot set the Board field to None and select a Part instead of a Board.

    When you select a Board, the Part field displays the name of the Xilinx device on the selected Board, and the Part setting cannot be changed.

  3. In the Compilation field, select Hardware Co-Simulation, and further select JTAG interface to perform hardware co-simulation.

    If the Hardware Co-Simulation option is grayed out and disabled, you cannot perform JTAG hardware co-simulation on the selected board.

  4. If you will use burst mode for a faster hardware co-simulation run, click the Settings button next to the Compilation field, select Burst mode, and enter a FIFO depth for the burst mode operation. Then click OK to close the Hardware Co-Simulation Settings dialog box.

    For a description of the burst mode, see Burst Data Transfers for Hardware Co-Simulation.

    Figure 2. Burst Mode
    Important: To perform a burst mode hardware co-simulation, you must create a test bench by checking the Create Testbench box in the System Generator token dialog box.
  5. If you want to create a test bench as part of the compilation, select the Create Testbench option.

    If you select Create Testbench, the compilation will automatically create an example test bench for you. You can also create your own test bench for hardware co-simulation (see M-Code Access to Hardware Co-Simulation).

  6. Click the Generate button.

    The code generator produces an FPGA configuration bitstream for your design that is suitable for hardware co-simulation. Model Composer not only generates the HDL and netlist files for your model during the compilation process, but it also runs the downstream tools necessary to produce an FPGA configuration file.

    The configuration bitstream contains the hardware associated with your model, and also contains additional interfacing logic that allows Model Composer to communicate with your design using a physical interface between the board and the PC. This logic includes a memory map interface over which Model Composer can read and write values to the input and output ports on your design. It also includes any board-specific circuitry that is required for the target FPGA board to function correctly.

    When the Compilation finishes the results are as follows:

    • If you have not selected Burst mode in step 4 above (standard mode), a JTAG Cosim hardware co-simulation block will appear in a separate window. Drag (or Copy and Paste) the Hardware Cosim block into your Simulink model. The Hardware Cosim block will enable you to perform hardware co-simulation from within the Simulink window.

      For a description of the hardware co-simulation block, see Hardware Co-Simulation Blocks.

      Figure 3. Hardware Co-Simulation Library Block

      If you selected the Create Testbench option for compilation, an M-Code HWCosim example test bench will also be generated (see M-Code Access to Hardware Co-Simulation) by the compilation. You can use this test bench to perform hardware co-simulation, or customize this test bench to develop a test bench of your own.

    • If you have selected Burst mode in step 4 above (burst mode), no hardware co-simulation block will appear. When you perform the burst mode co-simulation, you will use the MATLABĀ® M-code test bench placed in the target directory during compilation.
      • If you compiled the top-level design the test bench will be named:
      • If you compiled a subsystem of the design the test bench will be named:

      The compilation has prepared the Simulink model for performing hardware co-simulation.

      To perform the hardware co-simulation, proceed as follows: