In the example_dds design, Gateway In and Gateway Out
blocks mark the boundary of the Cycle and Bit accurate FPGA
portion of the Simulink
design. Control of the DDS Compiler frequency is accomplished by
“injecting” the correct value on the signals attached to the
output port of Gateway In’s called
phase_data. This is accomplished by
modifying the Interface Options, as shown below for the
As you can see, the Interface is specified as a slave AXI4-Lite Interface in Model Composer, which means that it will be transformed to a top-level AXI4-Lite interface.
The following options are also of particular interest:
Auto assign address offset (Enabled): Each Gateway is associated with a register within the AXI4-Lite Interface and this control specifies that Automatic assignment of address offsets will take place in the design based on number of different Gateway Ins mapped to the AXI4‑Lite interface. Addresses are byte aligned to a 32-bit data width.
Address offset (Disabled): This option is only enabled if Auto assign address offset is unchecked. It allows the user to manually override of Address Offset.
Interface Name: Assigns a unique name to this interface. This name can be used to differentiate between multiple AXI4-Lite interfaces in the design.
Description: The text you enter here is captured in the "Interface Documentation" that is automatically created when the design is exported to the Vivado IP catalog.
Configure the other Gateways in the design in a similar fashion.