When simulating PLIO with data files, the data should be organized to accommodate both the width of the PL block as well as the data type of the connecting port on the AI Engine block. Vitis Model Composer automatically generates the data file that accommodates to the specified PLIO width.
For example, a data file representing a 64-bit PL interface to an AI Engine kernel expecting
cint16 should be organized as
four columns per row, where each column represents a 16-bit real or imaginary value.
|PLIO Width||AIE Kernel Data Type||Dat File Layout|
This data file is in the output code directory.