IDE example project (
example_dds.xpr) is created to help you jump start your
usage of the IP created from Model Composer. This project is configured as follows:
- The IP generated from Model Composer is already added to the IP catalog associated with the project and available for the RTL flow as well as the IP integrator-based flow.
- The design includes an RTL instantiation of IP called example_dds_0 underneath example_dds_stub that indicates how to instance such an IP in RTL flow.
- The design includes a test bench called example_dds_tb that also instances the same IP in RTL flow.
- The design includes an example IP integrator
diagram with a
Zynq®-7000 Subsystem as the part
selected in this example is a
part. For all other parts, a MicroBlaze-based
Subsystem is created.Figure 1. IP Integrator Diagram
- If the part selected is the same as one of the supported boards, the project is set to the first board encountered with the same part setting.
- A wrapper instancing the block design is created and set as Top.
Tip: The interface documentation associated with the IP is accessible through the block GUI. To access this documentation, double-click the Model Composer IP, and click the Documentation button in the GUI.