Model Composer can automatically generate packaged IP for use in Vivado IP catalog. When Model Composer generates output for the IP catalog, it first writes the C++ code as described in Generating C++ Code, and then it synthesizes RTL code from the C++ code. This process begins when you set the Target in the Model Composer Hub block to IP catalog, hit Apply to confirm any changes, and click Generate.
Model Composer displays a transcript window of the process. When the process has concluded, the MATLAB® window displays the Synthesis Report for your review, as shown in the figure below. The Synthesis Report includes details on the estimated performance and resource utilization of the RTL design synthesized by Model Composer. You can review this report to see the estimates and review your model.
When Model Composer has completed synthesizing the RTL, it reports the
Exporting RTL as a Vivado IP to the transcript
window, and launches Vivado to create and package the IP for the subsystem design.
- SystemC (IEEE 1666-2006, version 2.2)
- VHDL (IEEE 1076-2000)
- Verilog (IEEE 1364-2001)
- Report files created during synthesis, C/RTL co-simulation, and IP packaging.
When Model Composer has completed generating the packaged IP, it can be found in the project directory structure as shown in the following figure. The Edge_Detection_IP folder is the Code Directory specified by the Model Composer Hub. The Edge_Detection_prj folder is a project created by the run_hls.tcl script. The solution1 folder is a Vitis HLS solution. For more information refer to the Vitis High-Level Synthesis User Guide (UG1399). The syn and impl folders store the results of synthesis and implementation. The ip folder contains the packaged IP to add to the Vivado Design Suite IP catalog.
After Model Composer has generated the packaged IP, the
.zip file archive in the <project_name>/<solution_name>/impl/ip folder can be imported into
the Vivado IP catalog, and used in any Vivado Design Suite design, either as RTL IP, or in the IP integrator.
For Model Composer models that specify AXI4-Lite Slave interfaces through the Interface Specification block, as discussed in Defining the Interface Specification, a set of software driver files is also created by Vitis HLS during the IP packaging process. These C driver files can be included in an SDK C project and used to access the AXI4-Lite Slave slave port. The software driver files are written to directory <project_name>/<solution_name>/impl/ip/drivers and are included in the packaged IP.
To add the IP into the Vivado IP catalog, from within the Vivado GUI, select the command to open the Settings dialog box. Select the command, and add the Vitis HLS packaged IP as shown in the following figure.
After adding the path to the repository, the IP is added to the IP catalog as shown in the following figure. You can now use the IP in standard RTL designs, or in Vivado IP integrator block designs. For more information on working with IP and adding to the IP repository refer to the Vivado Design Suite User Guide: Designing with IP (UG896).