HDL Testbench - 2022.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
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2022.1 English

Ordinarily, Model Composer designs are bit and cycle-accurate, so Simulink simulation results exactly match those seen in hardware. There are, however, times when it is useful to compare Simulink simulation results against those obtained from an HDL simulator. In particular, this makes sense when the design contains black boxes. The Create Testbench checkbox in the System Generator token makes this possible.

Suppose the design is named <design>, and a System Generator token is placed at the top of the design. Suppose also that in the token the Compilation field is set to HDL Netlist, and the Create Testbench checkbox is selected. When the Generate button is clicked, Model Composer produces the usual files for the design, and in addition writes the following:

  • A file named <design>_tb.vhd/.v that contains a test bench HDL entity.
  • Various .dat files that contain test vectors for use in an HDL test bench simulation.

You can perform RTL simulation using the Vivado Integrated Design Environment (IDE). For more details, refer to the document Vivado Design Suite User Guide: Logic Simulation (UG900).

Model Composer generates the .dat files by saving the values that pass through gateways. In the HDL simulation, input values from the .dat files are stimuli, and output values are expected results. The test bench is simply a wrapper that feeds the stimuli to the HDL for the design, then compares HDL results against expected ones.