Hardware Co-Simulation Compilation - 2022.1 English

Vitis Model Composer User Guide (UG1483)

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2022.1 English

Model Composer can compile designs into FPGA hardware that can be used in the loop with Simulink® simulations. This capability is discussed in the topic Using Hardware Co-Simulation.

As shown below, you may select Hardware Co-Simulation compilation by left-clicking the Compilation submenu control on the System Generator token dialog box, and selecting the Hardware Co-Simulation target.

Figure 1. Hardware Co-Simulation

The Board fields allows you to specify the development board you are targeting when you are performing the Hardware Co-Simulation compilation. You can only select a Board for Hardware Co-Simulation compilation - you cannot select a Part. When you select a Board, the Part field automatically displays the name of the Xilinx® device on the selected Board, and this part name cannot be changed.

JTAG Hardware Co-Simulation is supported for all Xilinx development boards.

The Simulink library (<design_name>_hwcosim_lib.slx) generated as part of a Hardware Co-Simulation compilation is placed in the directory you specified in the Target directory field. This library, and the hardware co-simulation block stored in the library, are described in Hardware Co-Simulation Blocks.