You can generate a hardware image for designs with only AI Engine blocks, or for designs with both PL and AI Engine designs. The following figure shows the topologies that are supported for Hardware Validation flow.
To generate the hardware image from a Simulink design, you should have an expandable platform. This is a file with the .xpfm extension. For Xilinx hardware, such as VCK190, the platform files are shipped with Vitis. You can also create an expandable custom platform for a custom board and use it in Vitis Model Composer. For more information refer to UG1393.
Using the Vitis Model Composer Hub block, you have a choice between creating a baremetal application or Linux-based application for either a hardware target or a hardware emulation target. In hardware emulation, Vivado simulator is used to simulate the PL portions of the design and QEMU is used to emulate the host code for the Arm processor. The advantage of hardware emulation is that there is no need for a hardware board. However, hardware emulation is only an emulation of the hardware and is, in general, slower than running the design in hardware.
As part of the creation of the hardware image, the input data samples that are fed into the design during simulation in Simulink are collected. Likewise, the output data samples from the design are also collected. The input and output data is packaged as part of the hardware image and downloaded to the hardware. The input data is fed into the design in hardware, the output data is collected and compared with the output data from simulation. This comparison is done by the processor in the device. Unless something is wrong, the result should match bit by bit with the result of the simulation because the simulation in Vitis Model Composer is bit accurate. The hardware runs independently of Vitis Model Composer, and during the hardware run no information is communicated between Vitis Model Composer and the hardware.