How to Use - 2022.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2022-05-26
Version
2022.1 English

Terminating Open Outputs

Consider the following model with open input and output ports:

Figure 1. Model with Open Input and Output Ports

Right-click the DDS Compiler 6.0 block in this case and select Xilinx Tools > Terminate > Outputs.

The following figure illustrates the resulting terminated outputs.

Figure 2. Terminated Output Ports

Terminating Open Inputs

Consider the following model with an open input port:

Figure 3. Model with Open Input Port

Right-click the DDS Compiler 6.0 block and select:

Xilinx Tools > Terminate > Inputs

The following figure illustrates the resulting terminated input.

Figure 4. Terminated Input Port