When a Model Composer model is to be included into a larger design, the following two design rules must be followed.
- Rule 1
- No Gateway or System Generator token should specify an IOB/CLK location.
Also, IOB timing constraints should be set to "none".
- Rule 2
- If there are any I/O ports from the Model Composer design that are required to be ports on the top-level design, appropriate buffers should be instantiated in the top-level HDL code.