Model Composer supports creation of IP with multiple AXI4-Lite interfaces. You can group Gateway In and Gateway Out blocks into different AXI4-Lite interfaces. This feature can be used in Multiple Clock designs as well. Software drivers will also be provided.
To assign a name to an AXI4-Lite interface, use the Interface Name control for the Gateway In and Gateway Out blocks associated with the interface.
All Gateway Ins and Gateway Outs with the same Interface Name are grouped into one AXI4-Lite Interface. An Interface Name must begin with a lower case alphabetic character, and can only contain alphanumeric characters (lowercase alphabetic) or an underscore ( _ ). Having the same Interface Name across multiple clock domains is not supported.
To generate the netlist you can use the IP Catalog or the HDL Netlist compilation target.
If you specify the HDL Netlist compilation target in the System Generator token, and then elaborate the design in Vivado, two AXI4-Lite Decoders will be created, as shown in red rectangle in the following figure.
If you specify the IP Catalog
compilation target in the System Generator token, the
flow will also generate an example BD with multiple AXI4-Lite interfaces and an
The naming convention for an interface is:
<clock domain name/design name>_<interface name>_s_axi
To generate a document describing the IP, select the Create interface document option on the System Generator Token Compilation tab before you perform the compilation.
Access the document the same way you access the document for any other Vivado IP. Double-click the IP in the Vivado schematic, then select .
A document (HTML file) will open up (see example below).