Setting the HDL-AIE Block - 2022.1 English

Vitis Model Composer User Guide (UG1483)
Document ID
UG1483
Release Date
2022-05-26
Version
2022.1 English

The following image depicts the components that are needed to connect an HDL design to an AI Engine subsystem. In setting this connection, you should consider certain input design criteria and set the parameters of the blocks accordingly. These input design criteria are:

  1. The bit width of the tdata signal line (W). This is the bit width of the data in the programmable logic.
  2. HDL design sample time (T). This sample time determines the target clock rate for which the HDL design will be clocked in hardware.
  3. The input data type to the AI Engine kernel block (DT). This is determined by the AI Engine kernel.
  4. The number of samples in the input to the AI Engine kernel block (S). For an AI Engine kernel with a window input type this is typically the size of the input window. For an AI Engine kernel with a stream input, this is typically the number of samples the AI Engine kernel consumes at every invocation.
  5. The period of all the input and output signals going into or out of the AI Engine subsystem (P). All the input and output signals of the AI Engine subsystem must have the same period.
Figure 1. Setting the HDL to AIE Block

Considering the five design criteria above, set the parameters of the blocks as follows:

Step 1: Set the PLIO bit width in the PLIO block

Set the PLIO bit width to W.

Step 2: Set the parameters of the HDL to AIE block

  • Set Output Data Type to DT.
  • Set Output frame size to S.
  • Set Output Sample Time to T x (bit width of DT)/(W) if this input is driving the AI Engine subsystem period or to P/S if the period of the AI Engine subsystem (P) is determined by another input to AI Engine subsystem.

Step 3: Set the Gateway Out AXIS block

Set the Sample Period parameter to the same value as in the corresponding Gateway In, AXI Stream block.