Bare-metal software drivers are created based on the address offsets assigned to the gateways. These drivers are located in the folder called <target_directory>/ip/drivers. <target_directory>/ip must be added to the Vitis™ environment search paths to use these drivers.
For each Gateway In mapped to an AXI4-Lite interface, the following two APIs are created.
/** * Write to <Gateway In id> of <design name>. Assignments are LSB-justified. * * @param InstancePtr is the <Gateway In id> instance to operate on. * @param Data is value to be written to gateway <Gateway In id>. * * @return None. * * @note <Text from Description control of the Gateway In GUI> * */ void <Gateway In id>_write(example_dds *InstancePtr, u32 Data); /** * Read from <Gateway In id> of <design name>. Assignments are LSB-justified. * * @param InstancePtr is the phase_valid instance to operate on. * * @return u32 * * @note Phase Valid Port That Must Be Asserted. * */ u32 <Gateway In id>_read(example_dds *InstancePtr);
<Gateway In id>:
<design_name> is the VHDL/Verilog top-level name of the design and
<gateway_name> is the scrubbed name of the
Gateway Outs generate a similar driver, but are read-only.