Step 1: Create a Connectivity Platform in Vivado as an IP Integrator Block Diagram (.bd) - 2022.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
Release Date
2022.1 English

First, you must create a block diagram containing your platform design in the Vivado® IP integrator. You may use a configurable example design, a reference design, or a custom-built design as the platform based system that will contain the accelerator part of the design.

In the example below, the platform design contains a Zynq®-7000 Processing System, and AXI DMA. The connectivity platform designer intends to transfer data to and from the DDR memory using the DMA, perform DES Encryption on the data received from the DDR, and then send the encrypted data back into the DDR. The AXI4-Stream ports M_AXIS_MM2S and S_AXIS_S2MM (Data Path) are made external to the Block Diagram (BD). It shows the intent of the platform designer that these interfaces are available for Model Composer to use during the Model Composer BD import process. An AXI4-Lite interface, M00_AXI, is also made external, indicating that there will be a control interface on the accelerator IP.

These are requirements for the design in the IP integrator:

  • This system has to be built for a specific board or part. This ensures that certain ports and interfaces have known location attributes assigned to them.
  • The AXI Interfaces that you want to bring into the accelerator portion of the design have to be made external.
Figure 1. AXI Interfaces

Currently Xilinx supports the following interfaces from the platform framework point of view:

Table 1. Supported AXI Interfaces
Interface Master Slave
AXI4 Yes No
AXI4-Lite Yes No
AXI4-Stream Yes Yes