Synthesized Checkpoint Compilation - 2022.1 English

Vitis Model Composer User Guide (UG1483)

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2022.1 English

Vivado tools provide design checkpoint files (.dcp) as a mechanism to save and restore a design at key steps in the design flow. Checkpoints are merely a snapshot of a design at a specific point in the flow. A Synthesized Checkpoint is a checkpoint file that is created in the out-of-context (OOC) mode after a design has been successfully synthesized.

When you select the Synthesized Checkpoint compilation target (see figure below), a synthesized checkpoint target file named <design_name>.dcp is created, and placed in the Target directory. You can then use this <design_name>.dcp file in any Vivado IDE project.

Figure 1. Synthesized Checkpoint

The Board and Part fields allow you to specify the board or part for which you are targeting the Synthesized Checkpoint compilation. When you select a Board, the Part field automatically displays the name of the Xilinx device on the selected Board. This part name cannot be changed.

The Synthesized Checkpoint compilation can be performed for any of the boards or parts your Vivado tools support. In addition to accessing the Xilinx development boards installed as part of your Vivado installation, you can also specify partner boards or custom boards (see Specifying Board Support in Model Composer HDL Blockset).