When the Target specified on the Block Parameters dialog box of the Model Composer Hub is either IP Catalog or System Generator, and the verification flow is enabled, Model Composer uses C/RTL co-simulation to verify the RTL output. Again, the objective is to verify that the results of the RTL simulation match the results of the Simulink simulation. In this case, the verification flow is as follows:
- The Model Composer model is simulated in Simulink to capture the test vectors in signals.stim.
- Model Composer generates the C/C++ code and the C test bench, tb.cpp.
- Model Composer runs the C-synthesis and generates the RTL output.
- Model Composer runs the C/RTL co-simulation. This step ensures the
- That the C++ code generated by Model Composer is correct by comparing with the Simulink simulation, signals.stim.
- That the RTL code generated by Model Composer is correct by
comparing the output stimulus from RTL with C/C++ output.Tip: After verification, Model Composer exports the RTL as an IP for Model Composer HDL model, or packages the IP for use in Vivado.
- The result is a separate Pass/Fail returned by Model Composer for both the C-simulation and the C/RTL co-simulation. If the C-simulation fails, the process stops before the C/RTL simulation is run.