As indicated earlier,
support for fixed-point data types through the Fixed-Point Designer™ product. However, the
format of the
fixed data type supported by Model Composer and
Simulink are not compatible.
The format used to display the Model Composer fixed-point data types is as
x_: Is the prefix indicating the Xilinx fixed data type.
[u/s]: Represents signed or unsigned data.
fix: Indicates the fixed-point data type.
[wl]Specifies the word length of the data.
E: Prefix for the fractional portion of the fixed-point data type. Does not display if the fractional length is 0.
n: Displays 'n' if the binary point is to the left of the right-most bit in the word; or displays no 'n' if the binary point is to the right of the right-most bit in the word.
[fl]: Specifies the fractional length of the fixed-point data type, indicating the position of the binary point with respect to the right-most bit in the word.
x_sfix16_En6 represents a
signed 16-bit fixed-point number, with 6-bits allocated to the right of the binary point.
Notice the fixed-point data type also lets you specify what happens in the case of data overflow, or the need to do rounding or truncation. For more information refer to Data Type Conversion.
- Convert Model Composer fixed-point data type to the
doubledata type using the DTC block from the HLS library in the Library Browser.
- Convert the
doubledata type to Simulink format fixed-point data type using the Simulink Data Type Conversion block from the Simulink Signal Attributes library in the Library Browser.
- Match the signedness, word length, and fractional length between the two fixed-point data types.
Although handling fixed-point data type in a design is more time consuming, the value of using fixed-point data types for applications targeted at implementation in an FPGA is worth the challenge. It is widely accepted that designing in floating point leads to higher power usage for the design. This is true for FPGAs where floating-point DSP blocks have been hardened onto the FPGA and users must implement a floating point solution using DSP blocks and additional device resources. Floating-point implementations require more FPGA resources than an equivalent fixed-point solution. With this higher resource usage comes higher power consumption and ultimately increased overall cost of implementing the design. For more information refer to the white paper Reduce Power and Cost by Converting from Floating Point to Fixed Point (WP491).